The invention pertains to the manufacture and testing of semiconductor integrated circuits. More particularly, the invention pertains to the manufacture and testing of dynamic random access memories.
In order to reduce the failure rate of integrated circuits while in actual operation, it is desirable that each circuit be put through a burn-in procedure prior to the use of the circuit in operating electronic equipment. The simplest way to conduct the burn-in procedure is to connect the integrated circuit to power supply sources of the intended ratings of the circuits in a test circuit while, for instance, clocking predetermined test data in and out of the memory. However, such a burn-in procedure is not efficient because only a relatively small proportion of potential failures will show up within a reasonable burn-in time of, for example, one hour or less.
In order to accelerate the burn-in procedure, it is well known to conduct the procedure at an elevated temperature. This does increase the number of failures which show up during a procedure of reasonable length. However, there are limits on the temperature of the device above which irreparable damage is done to the device.
Another known technique for accelerating the number of defective devices which can be detected during a burn-in procedure is to increase the operating voltages applied to the circuit. Such a technique, known as voltage stressing, is described in Intel Corporation Reliability Report RR-7, September 1975. As indicated by the graph of FIG. 3 thereof, the failure rate of a batch of dynamic random access memories in a burn-in procedure can be dramatically increased by increasing the applied operating voltage. If, for example, the applied operating voltage is increased to one and one-half to two times the normal operating voltage, the failure rate during the burn-in procedure can be more than doubled.
Although the above-described conventional method of increasing the operating voltage can be used for many types of devices, as the cell size of a random access memory is decreased, increasing the operating voltage tends to destroy devices which are "good" devices and which should not show up as failures during the burn-in procedure. For instance, in a 4K dynamic random access memory using four micron photolithography, it is possible to apply a V.sub.DD operating voltage in the range of one and one-half to two times the normal V.sub.DD level without damage to the device. However, for a 64K memory in which two micron photolithography is utilized, increasing V.sub.DD above one and one-half times the normal level will damage many otherwise normal devices. The reason for this is that the reduced size of the transistor devices used in the memory reduces the sustaining voltages of the devices above which junction damage or drain-to-gate oxide shorting occurs.
Hence, it is an object of the present invention to provide a dynamic random access memory which can be put through a burn-in procedure in a relatively short period of time, while yet it is possible to detect a large portion of defective devices during the burn-in procedure.
It is a further object of the invention to provide such a random access memory having a small cell size which is capable of sustaining an elevated operating voltage during a burn-in procedure without damage to transistor devices of the memory.
Still further, it is an object of the invention to provide a burn-in method for random access memories having a small cell size with which a large portion of defective devices can be detected within a reasonable test time without damaging normal devices.